Examination of Interconnects in Semiconductor Device

Introduction

Since the development of integrated circuits (IC) about 60 years ago, aluminium (Al) and silicon dioxide (SiO₂) have been most widely used as conductor and insulator materials, respectively, for the fabrication of microprocessors. The dimensions of integrated circuits are scaling down in order to achieve better electrical performance, but so-called gate delays are limiting device performance. When the signal is applied to the gate input, some time is needed to respond to the change, for the output to reach a stable value consistent with the inputs. Even with the perfect conductor, it takes time for the electrical signal to propagate, so any kind of capacitive effect within the gate will slow this response. Gate delays are important because they determine how fast a circuit works. To overcome this problem, new wiring materials with resistivity lower than Al, and dielectric materials with dielectric constants (so-called low-k) lower than conventional SiO₂, have to be used as alternatives. Cu interconnects are used as internal wiring in chips connecting different parts of the circuit and distributing power. Cu has a smaller gate delay compared to Al due to its lower electrical resistance, but also higher electro-migration, stress-migration resistance, and melting point. Nowadays, film interconnections are becoming the limiting factor in determining performance and reliability of integrated circuits.

Challenge

There are different challenges in using Cu. It is a fast diffusion species in silicon oxide and silicon causing deep-level trapping which seriously degrades the electronic properties of devices, it is susceptible to oxidation, corrosion and is highly chemically reactive. A diffusion barrier against copper is also needed and plays a major role in Cu metallisation. Tantalum is often the choice for a diffusion barrier as Ta and Cu are mutually insoluble and Ta exhibits low resistivity. The structure of Cu interconnects is usually patterned by a so-called damascene process, in which the dielectric layer is patterned in advance, followed by the sequential deposition of a diffusion barrier layer and the filling of the patterned trenches with Cu. The next generation devices demand the continuous decrease of feature sizes, which consequently increases the difficulty of defect-free filling of the trenches in the damascene process. Another challenge is to achieve uniform deposition of the ultra-thin film on the dielectric layer.

Aim

The problem when analysing these structures is their size, so they require high resolution capability in order to map different components. Using SEM-EDS, it is possible to inspect if there is any degradation of devices due to the diffusion of Cu into the Si, any discontinuity in the barrier layer, incomplete filling, or poor adhesion of the barrier layer. Barrier layers are extremely thin, so to achieve adequate resolution, a STEM approach of analysing thin lamella sample using Ultim Max 100 or Ultim Max 170 detectors is the best solution.

Results

1. Bulk Cross-section

Figure 1 displays a common problem in mapping this type of structure, when we are trying to map a bulk sample in a short amount of time (in this example, in 4 min). The spatial resolution is not sufficient to observe different layers and gain the right conclusion about the distribution of thin layers. In addition to the limitation of spatial resolution when analysing a bulk sample, the energy overlap between the high intensity Si signal and the lower intensity Ta signal means the maps are essentially showing the same distribution, which is dominated by Si. One solution is to process and separate the overlapping Si and Ta signals using the deconvolution mapping software TruMap. A TruMap calculated using this software shows the distribution of Ta, and it is possible to obtain some information about the Tantalum distribution. However, the Ta signal is low compared to the background noise, and so the Ta layer is not clearly displayed.

Figure 1: EDS mapping of bulk cross-section from the semiconductor device using an Ultim Extreme detector at 5 kV 800 pA. Top row shows the sample topography and phase contrast in the electron image, and the window integral count maps for Ta and Si. The bottom row shows the overlap corrected Ta signal in the Ta TruMap.

2. Lamellae Cross-section

In order to further improve spatial resolution, a thin lamella sample was prepared from the semiconductor device. A STEM-SEM approach (Figure 2) uses a high beam energy of 30 kV to minimise the interaction of the electron beam with the sample and maximise the spatial resolution of the X-ray signal. However, due to the thin nature of the sample, there is a significant reduction in X-ray count rate. To compensate for this reduction in X-rays, an EDS detector with a larger area sensor is required, such as an Ultim Max 100 or Ultim Max 170, to provide useful elemental information in a reasonable time frame.

Figure 2: Lamella from semiconductor sample attached to the grid. Left, low magnification secondary electron image, arrow pointing towards lamella. Right, higher magnification image acquired using FSD diodes from the EBSD detector showing analysed area in orange rectangle.

Figure 3 shows the result of a 10 minute map acquisition with Ultim Max 100. The copper interconnects are seen in orange in the Cu map and the tantalum barrier structures in blue in the Ta map. Using this approach, the tantalum layer is much more distinctly displayed and the signal to noise is much higher compared to results obtained using the bulk sample in Figure 1.

Figure 3: STEM-EDS mapping of interconnect and barrier layers using an Ultim Max 100 detcctor at 30 kV and 5 nA. Layered image with Cu and Ta maps overlaid on the secondary electron image, and Ta and Cu layer maps.

Close inspection of the Ta layer map shows areas of high signal that are not due to the Ta barrier. As with the bulk sample above, the Ta map shows signal from the overlapping energy signal of Si (Figure 4).

Figure 4: Sum spectrum from the area mapped in Figure 3. The Si and Ta signals overlap in the same peak, due to similar energies of TaMa and SiKa X-ray lines.

Processing of the maps using TruMap to separate the spectral overlaps again removes the false information from the maps. The TruMaps (Figure 5) reveal the same type of information as the integral maps but give extra confidence about the barrier layer distribution. From these maps it is possible to conclude that the barrier layer is thicker on the bottom of the contact and thinner on the sides.

The mapping results are also important because they will reveal if there are any problems during manufacturing of the device and which step could be problematic. It is also possible to assess if there is any diffusion of the Cu into other parts of the device, if there is good adhesion of the barrier layer, or if there are any voids in the Cu interconnects. These maps show that the deposition of ultra-thin Ta film is relatively uniform without any voids in the Cu.

Figure 5: STEM-EDS TruMap of the interconnect structure calculated from the data collected using 30 kV 5 nA with Ultim Max 100.

Conclusion

STEM-EDS analysis of a thin lamellae can be used to achieve better spatial resolution, in a reasonable time-frame, when EDS data is collected using a large sensor area EDS detector such as Ultim Max 100. The STEM approach can be used to optimise deposition methods to assess uniformity and chemistry of the deposited ultra-thin film on the dielectric layer. It can also aid in finding a suitable replacement for traditional barrier materials, such as in the study of PGM-based materials Ru, Ir, Pd and their composites, or other materials e.g. High-Entropy Alloys. This approach can also be helpful in reverse engineering, patent infringement cases or general R&D, Q&C in the semiconductor industry.